Question 1: We wish to build a 3-bit synchronous counter using edge-triggered J-K flip-flops with outputs Q3, Q2, and Q1

[answerhappygod]

Question 1 We Wish To Build A 3 Bit Synchronous Counter Using Edge Triggered J K Flip Flops With Outputs Q3 Q2 And Q1 1 (50.39 KiB) Viewed 45 times

Question 1: We wish to build a 3-bit synchronous counter using edge-triggered J-K flip-flops with outputs Q3, Q2, and Q1. A schematic diagram (minus the logic for the flip-flop inputs) is shown below: J1 J2 Q2 CLK с J3 Q3 C K1 с K2 K3 The counter must output the following sequence of decimal numbers in 3-bit binary and then repeat: 1—6—4—3—5—2 .... The output of the counter is Q:Q2Q1. If the counter starts or gets into an illegal state it should return to 1 after the next clock pulse.

(b) Work out the optimized sum of products logical expressions for the flip-flop inputs J2 and K2.