Question 6 (20%): A row-address decoder is shown below. This decoder is supposed to decode one address into one unique r

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Question 6 20 A Row Address Decoder Is Shown Below This Decoder Is Supposed To Decode One Address Into One Unique R 1 (90.24 KiB) Viewed 46 times

Question 6 20 A Row Address Decoder Is Shown Below This Decoder Is Supposed To Decode One Address Into One Unique R 2 (44.71 KiB) Viewed 46 times

Question 6 (20%): A row-address decoder is shown below. This decoder is supposed to decode one address into one unique row. RO + R1 HE R2 . + R3 바로 tout R4 HE R5 R6 R7 Āz Az Az Aų Az à A1 Ao Ao Row address

(a) Complete the following table based on the logic values given to the input row address lines. (9%) Αο Α1 Α2 Row selected (stayed at VDD) (RO through R7) 0 1 0 1 0 1 0 1 A1 A2 0 0 0 0 1 0 1 0 0 1 0 1 1 1 1 1 (5%) (b) Identify the row addresses (A, A1 A2) that were decoded correctly. A, A1 A2 = c) Based on circuit below: (6%) a A B b 9 DoiD F b W с u D d 1 What is the test pattern required to test stuck-at-1 fault at noder? ABCD = (11) What is the test pattern required to test stuck-at-o fault at node w? ABCD = =