Question 5 20 A For The Memory Cell Shown In Figure Below Assume That Vpp 1 2v Vin 0 3v If At Time T To Bit 1 (33.8 KiB) Viewed 47 times
Question 5 20 A For The Memory Cell Shown In Figure Below Assume That Vpp 1 2v Vin 0 3v If At Time T To Bit 2 (32.27 KiB) Viewed 47 times
Question 5: 20% a) For the memory cell shown in Figure below, assume that Vpp = 1.2V, VIN = 0.3V. If at time t = to. Bit line was charged to 0.6V and Word line was set to OV. Then at time t = t. (t. >to). Word line was turned on, set to 1.2V. Measurements indicate that there was Bit line voltage change after t.. Word line Cs Bit line CH Cell (1) What is the logic value stored in if the Bit Line voltage is 0.75V after t;? (19) 1/0 (11) Compute the value of Cs/Cg ratio. (3%) (iii) Compute the value of Cs in term of fF if Cz=0.4pF. (3%) (iv) To store a logic 1 (VDD) to the memory cell, what are the required word line voltage and bit line voltage for transistor Q, respectively. (3%) Word line voltage = Bit line voltage = V
(6) The layout below belongs to a NAND flash structure. In order to read the content stored in the highlighted transistor, label every transistor gate with the necessary gate voltage (Voi Vin, Von) in the NAND structure shown below. (5%) GND Bit Line N (d) How many bits of memory can be stored in the NAND flash structure shown above if each transistor can possibly have 4 different threshold voltages? (2%) (e) To increase the flash memory storage density, what can be done to the floating gate transistor device characteristics? (2%) (1) NOR flash memory chips provide higher density and higher storage capacity than NAND flash memory chips. (1%) True / False
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