1-2. Create a two-bit wide 2-to-1 multiplexer using gate-level modeling. 1-2-1. Open PlanAhead and create a blank projec

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1 2 Create A Two Bit Wide 2 To 1 Multiplexer Using Gate Level Modeling 1 2 1 Open Planahead And Create A Blank Projec 1 (35.12 KiB) Viewed 84 times

1-2. Create a two-bit wide 2-to-1 multiplexer using gate-level modeling. 1-2-1. Open PlanAhead and create a blank project project called lab1_1_2. 1-2-2. Create and add the Verilog module with two 2-bit inputs (x[1:0), y(1:0), a one bit select input (s), and two-bit output (m[1:0) using gate-level modeling. 1-2-3. Create and add the UCF file to the project. Assign SWO and SW1 to x[1:0), SW2 and SW3 to y(1:0), SW7to s, and LEDO and LED1 to m[1:0). 1-2-4. Synthesize the design. 1-2-5. Implement the design. 1-2-6. Generate the bitstream, download it into the Nexys3 board, and verify the functionality.