2 20 Pts A Sequence Detector Is To Be Designed To Detect Both The Sequence 0101 And 1011 Simultaneously You Will Dev 1 (49.23 KiB) Viewed 117 times
2 20 Pts A Sequence Detector Is To Be Designed To Detect Both The Sequence 0101 And 1011 Simultaneously You Will Dev 2 (27.35 KiB) Viewed 117 times
2. [20 pts) A sequence detector is to be designed to detect both the sequence 0101 and 1011 simultaneously. You will develop a state diagram with one input variable X and one output variable 2. The output is 1 if and only if the last four input bits are either 1011 or 0101. Note that sequences may overlap. Sample input: 0010101101101101010 Sample output: 0000101100100100010 A) [8 pts] Draw the state diagram. Label each arc with XZ. Label the initial state with So and other states with S. Sz. Ss, etc. Use a minimum number of states. Please use Mealy model. You can draw the state diagram on a white paper, and then, take a photo of it. Next, you can insert the photo here. Hint: you only need to use 7 states. Start S. B) (4 pts) Implement this state diagram using the minimum number of D flip- flops. Complete the following state table for this state diagram. Assume that we use the following state assignments: So=000, S1 = 001, S =010, S: 5011, Si=100, Ss = 101, S6 = 110, S==111. Note that you might not need all of the 8 states. Please use don't cares conditions for unused states. Q. QOX Q(+1) Q (t+1) Qu(t+1) Z
C) [4 pts] Complete the following four K maps using the K-map template below. And then derive optimized Boolean expressions for the inputs to the D flip-flops and the output of the sequential circuit. Note that D, stands for Q2(t+1). Similarly, D stands for Qi(t+1) and Do stands for Qo(t+1). D: D: D: Z: D> D D. Z- D) [4 pts) Draw the logic diagram of the circuit. 이 D b D 여
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