21. Complete the Verilog design for a D flip-flop with high active asynchronous reset module mydff(clk,reset,0,0); input

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21 Complete The Verilog Design For A D Flip Flop With High Active Asynchronous Reset Module Mydff Clk Reset 0 0 Input 1 (30.46 KiB) Viewed 82 times

21 Complete The Verilog Design For A D Flip Flop With High Active Asynchronous Reset Module Mydff Clk Reset 0 0 Input 2 (21.78 KiB) Viewed 82 times

21. Complete the Verilog design for a D flip-flop with high active asynchronous reset module mydff(clk,reset,0,0); input cik, reset,D; output rega always @(posedge clk, 1 if L2 Q<=0; else Q<=D; a. negedge reset (1) b. negedge reset (1) C. posedge reset (1) d. posedge reset (1) -reset (2) reset (2) reset (2) reset (2) 22. Complete the verilog design to implement a T flip-flop using a JK flip-fop module mydffclk,T,Q); input clk, T; output : jkffo u/clk, endmodule a); module jkffo (clk, J, K, Q); input clk, , K; output reg Q: always @[posedge clk) case 2 0:Q<=_3 1:Q<=0; 2:Q<=1; 3: Q<="Q; Endcase endmodule a. TT (1) J, K (2) b. , -T (1) U.K) (2) c. T,T(1) {JK) (2) d. T,"T(1) J, K (2) e. "T,T (1) J, K2) 0 (3) Q(3) Q(3) 1(3) Q13)

Auke a decade counter that counts o through 9, inclusive. The reset input is synchronous, and to 9. should reset the counter to 0. The counting sequence is 0, 1,2,..., 9 and then it repeats from o module decadeCounter Input clk, input reset, output reg (3:0) : always @[posedge clk) if (reset) qc1 else if 2 q<+1; else 3 endmodule 23. The statement for blank 1 is (a) 1 (b) 2 (c) 3 (d) o 24. The statement for blank 2 is (a) q<10 (b) qc 10 (c) q<9 (d) qc=9 25. the statement for blank 3 is (a) q<=46'0000 (b) qcu4b0000 (c) qc-4b'0000 (d) q>4'60000