2. Assume the unity feedback system shown below Reference Input Controller Output Plant 1 with analog plant G(S) = and d

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2 Assume The Unity Feedback System Shown Below Reference Input Controller Output Plant 1 With Analog Plant G S And D 1 (150.97 KiB) Viewed 67 times

2. Assume the unity feedback system shown below Reference Input Controller Output Plant 1 with analog plant G(S) = and design an analog controller of the form (50 Points] (s+1)(s+5) K(s+zlead )(s+zlag) C($)= to simultaneously yield the following time domain specifications to (s+ Piead)(s+ Plag) a step input: f) Zero steady-state error g) 2% settling time to 0.8 seconds h) Percent overshoot equal to 4.3% 3. Discretize the controller of Problem #2 using a forward difference with a sample period of T = 0.1s and assuming the control topology shown below. Predict the steady state error to a unit ramp unit. (50 Points] R(2) E(2) U(z) Y(z) C(2) DAC G(S) ADC GZAS (2)