· [3 Grades) Research Question: Consider the following two modules. The first module represents synchronous reset while

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3 Grades Research Question Consider The Following Two Modules The First Module Represents Synchronous Reset While 1 (52.37 KiB) Viewed 70 times

· [3 Grades) Research Question: Consider the following two modules. The first module represents synchronous reset while the other represents asynchronous reset. What is the difference between the two types of reset? Justify your answer with a timing diagram. module async_rst(clk, rst, a, b); module sync_rst (clk, rst, a, b); input clk, rst; input clk, ist; input a; input a; output reg b; output reg b; always @ (posedge clk, posedge rst) always @ (posedge clk) begin begin if (rst == 1) if (rst == 1) b<=0; b<=; else b<=a; b<=a; end end endmodule endmodule else