- 17 The 74195 In 17 Is A Synchronous Tod 4 Bit Paralleless Shift Register For This Exercise The Input Data Is Loaded A 1 (24.93 KiB) Viewed 33 times
17. The 74195 in 17 is a synchronous tod, 4-bit paralleless shift register. For this exercise the input data is loaded a
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17. The 74195 in 17 is a synchronous tod, 4-bit paralleless shift register. For this exercise the input data is loaded a
17. The 74195 in 17 is a synchronous tod, 4-bit paralleless shift register. For this exercise the input data is loaded at the first active clock edge (12 pes 20195 OSIM SHILD 1 Is 14 ОА Q Ох A B 5 0 OD 11 D OD DSTMI 10 CLK CLR Figure 17 Use the circuit of Figure 17 to answer the following questions: Is this a ring counter or a Johnson counter? (2 pts) b. How many different states are available? (2 pts) c: Draw the timing diagram (four clock pulses) for the input as shown in the figure above. Use the space provided below. The timing diagram should include only the clock and the valid outputs. (6 pts) (Hint: First, generate the truth table of clock pulse and the valid outputs) d. What is the duty cycle for each output line? (2 pts)
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