[20 marks] Refer to the single-cycle processor architecture
shown below, what will be the values of these control signals
(RegDst, ALUSrc, MemtoReg, Branch, and Jump) when the following
instructions are executed.
(a) and $t0, $t1, $t2
(b) addi $t0, $t1, 100
(c) lw $t0, 100($t1)
(d) sw $t0, 100($t1)
20 Marks Refer To The Single Cycle Processor Architecture Shown Below What Will Be The Values Of These Control Signal 1 (200.93 KiB) Viewed 56 times
4. [20 marks] Refer to the single-cycle processor architecture shown below, what will be the values of these control signals (RegDst, ALUSrc, MemtoReg, Branch, and Jump) when the following instructions are executed. Jump address (31-0) Instruction (25-0) Shift left 2 26 28 PC +4 [31-28] M M Add u х 4 >Add ALU result Shift left 2 Instruction (31-26) RegDst Jump Branch MemRead Memto Reg Control ALUOP Mem Write ALUS RegWrite Read PC register 1 Read Instruction (25-21] Read address Instruction (20-16] Instruction (31-0) Instruction Instruction [15-11) X memory Read data 1 register 2 Write Read Zero > ALU ALU Address Read U result data register data 2 M exes Write 1 data Registers Write Data data memory Instruction (15-0 16 Sign- 32 extend ALU control Instruction (5-0) (a) and (b) addi (c) lw (d) sw $t0, $t1, $t2 $to, $t1, 100 $t0, 100($t1) $t0, 100($t1)
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