Consider the following assembly language code: I0: add $t1,$s0,$t4 I1: add $t1,$t1,$t5 I2: lw $s0, value I3: add $s

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Consider the following assembly
language code:
I0: add $t1,$s0,$t4
I1: add $t1,$t1,$t5
I2: lw $s0, value
I3: add $s1,$s0,$s1
I4: add $t1,$t1,$s0
I5: lw $t7,($s0)
I6: bnez $t7, loop
I7: add $t1,$t1,$s0
Consider a pipeline with forwarding,
hazard detection, and 1 delay slot for branches. The pipeline is
the typical 5-stage IF, ID, EX, MEM, WB MIPS design. For the above
code, complete the pipeline diagram below (instructions on the
left, cycles on top) for the code. Insert the characters IF, ID,
EX, MEM, WB for each instruction in the boxes. Assume that there
two levels of forwarding/bypassing, that the second half of the
decode stage performs a read of source registers, and that the
first half of the write-back stage writes to the register file.
Label all data stalls (Draw an X in
the box). Label all data forwards that the forwarding unit detects
(arrow between the stages handing off the data and the stages
receiving the data). What is the final execution time of the
code?

Consider The Following Assembly Language Code I0 Add T1 S0 T4 I1 Add T1 T1 T5 I2 Lw S0 Value I3 Add S 1 (16.74 KiB) Viewed 71 times

TO T1 T2 T3 T4 T5 T6 T7 00 T9 T10 T11 T12 T13 T14 T15 T16 add $t1,$ 50, $t4 IF ID EX MEM WB add ptl,#t,#t5 IF ID EX MEM WB lw $50, value IF ID EX MEM WB add $sl, $50, $sl IF ID EX MEM WB add htl, tl, 50 IF ID EX MEM WB lw $t7, ($80) IF ID EX MEM WB bnez $t7, loop IF ID EX MEM WB add #t1, tl, 50 IF ID EX MEM WB