b. [15pts] Consider the previous MIPS code executed on a pipelined processor with a 5-stage pipeline, forwarding mechani

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B 15pts Consider The Previous Mips Code Executed On A Pipelined Processor With A 5 Stage Pipeline Forwarding Mechani 1 (494.59 KiB) Viewed 48 times

b. [15pts] Consider the previous MIPS code executed on a pipelined processor with a 5-stage pipeline, forwarding mechanism, and this time assume 2nd branch is taken. Please fill the pipeline diagram. Here, we assume there are no delay slots and that branch outcomes are determined at the ID stage. The first scheduled instruction is given as an example. **** indicates pipeline stalls. 6 7 3 8 9 10 13 12 14 16 15 17 1 F 2 D 4 5 M W this loop: sit $t0,$s 1, $s2 beg $t0 $0, end add $t0,$s3. Ss4 lw $t0,($t0) beq Sto. $0, afterif sw $50.0(St0) addi Ss0. Ss0.1 afterif; addi Ssl. Ss1.1 addi Ss4. Ss4.4 loop end: add $v0, S80. SO