[25 pts] For all the following questions we assume that: a) Pipeline contains 5 stages: IF, D, EX, MEM and WB; b) Each s

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25 Pts For All The Following Questions We Assume That A Pipeline Contains 5 Stages If D Ex Mem And Wb B Each S 1 (490.38 KiB) Viewed 29 times

[25 pts] For all the following questions we assume that: a) Pipeline contains 5 stages: IF, D, EX, MEM and WB; b) Each stage requires 1 clock cycle. c) All memory references will hit in cache. a. [10pts] Consider the following MIPS code executed on a pipelined processor with a 5-stage pipeline, forwarding mechanism, and assume neither branch is taken. Please fill the pipeline diagram. Here, we assume there are no delay slots and that branch outcomes are determined at the ID stage. The first scheduled instruction is given as an example. «*** indicates pipeline stalls. 3 6 7 8 9 ON 10 12 13 15 16 17 1 F 2 D 4 M 5 W loop: sit Sto. $$1. Ss2 beq Sto. SO, end add Sto. Ss3. Ss4 lw $t0.0(Sto) beg Sto. $0, afterif Sir Ss0.0(St0) addi Sso. Ss0.1 afterif; addi Ss1. Ss1.1 addi Ss4, S54.4 j loop end: add $10. SsO. SO