Assume that the following instruction sequence executes on a CPU with a 5 stage pipeline. The CPU does not have operand

[answerhappygod]

Assume that the following instruction sequence executes on a CPU
with a 5 stage pipeline. The CPU does not have operand forwarding
or branch prediction. Identify any hazards in the code and suggest
at least one way that hazards can be resolved.
MOV R4,#0
MOV R3,#9
STR
R2,[R1],#4
loop: ADD R4,R4,R5
SUBS
R3,R3,#1
BNE loop
STR R4,[R1]