G In The Following Table Show The Pipelined Execution Of These Instructions In The Order Given Assuming The Machine S 1 (62.96 KiB) Viewed 35 times
g) In the following table, show the pipelined execution of these instructions in the order given, assuming the machine shown below in Figure 5, by writing the name of the pipeline stage (IF, ID, EX, MEM, or WB) for each instruction and each clock period. Leave the box blank for each clock period in which no stage is active for any instruction. Assume the register file can be written and read in the same clock cycle. Instruction CP1 CP2 CP3 CP4 CP5 CP6 CP7CP8 CP9 CP10 CP11 C
1. [30 points] This problem pertains to the following sequence of MIPS instructions: ; # and yes the 2 is a number Instruction Address Ox24 Ox28 0x2C Ox30 Ox34 Ox38 Instruction add $1, $2, $1 beq $1, $3, 2 nop add $12, $2, $2 add $13, $12, $2 sw $13, 10 ($10)
PIPELINED DATAPATH WITH CONTROL Branch IF Flush ID Flush EX.Flush ID/EX 80000080 EX/MEM MEM/WB Cause Except PC ALUSIC Shift left 2 Instruction memory Data memory Read Head oster 1 data 1 Read register 2 Registers register Read Write data 2 data MemtoReg nstruction wite ALU Address Read data Address Read! data Write data KE 16 32 MemRead Sign extendi ALUOD RegDst Instruction (25-21] Instruction (20-16] Instruction (20-16] Instruction (15-11]
Join a community of subject matter experts. Register for FREE to view solutions, replies, and use search function. Request answer by replying!