Q3 For The Following Datapath And Control Design Br 1 Inse Mem Register Fle 51 52 Dl Data Mem Rwd X Rwe 0 Aluop 1 We 1 (29.36 KiB) Viewed 59 times
Q3 For The Following Datapath And Control Design Br 1 Inse Mem Register Fle 51 52 Dl Data Mem Rwd X Rwe 0 Aluop 1 We 2 (14.07 KiB) Viewed 59 times
Q3: For the following datapath and control design: BR=1 @ Inse Mem Register Fle 51 52 dl Data Mem RWd=X Rwe=0 ALUOP=1 we=0 Rdst=X ALUinB=0 (a) What is the instruction that this datapath will execute taking into consideration the provided control signals?
(b) What is the two possible addresses that can be stored in the PC register after the execution of this instruction? (c) Why the Rdst and Rwd control signals are not used (don't care) in this instruction?
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