- 1 Objectives In This Lab You Need To Implement The Single Cycle Risc V Processor With Hardware Description Language H 1 (274.55 KiB) Viewed 21 times
1. Objectives In this lab, you need to implement the single-cycle RISC-V processor with Hardware Description Language (HDL) code that supports the subset instructions. 2. Subset of the RISC-V Instructions Required for the Designed Processor The designed single-cycle processor only implements a subset of RISC-V instructions. This subset instructions are sufficient to illustrate the design of datapath and control unit and the required subset includes the following instructions: R-type instructions: add, sub, and, or, sit I-type instructions: addi Memory instructions: Iw, sw Branch instruction: beq J-type instruction: jal . . 3. Generic Building Blocks This section lists some generic building blocks that may be useful in any digital system, including adder, extend unit, flip-flops with write enable, multiplexer, and etc. 4. The main modules 1) Main Decoder: decoder the opcode and generate control signals including RegWrite, MemRead, MemWrite, ALUSrc, ALUOp and etc. 2) ALU Decoder: generate ALU Operation code with ALUOp, funct3, and funct7. 3) Controller, which include main decoder, ALU decoder and PCSrc. 4) Instruction memory 5) Data memory 6) Datapath 7) Single-cycle processor 5. Testbench The testbench loads a program into the memories. The below program exercise all of the instructions by performing a computation that should produce the correct result only if all of the instructions are functioning correctly. Specially, the program will write the value 25 to address 100 if it runs correctly. . text main: addi x2, x0, 5 addi x3, x0, 12 addi x7, x3, -9 or x4, x7, x2 and x5, x3, x4 add x5, x5, x4 beg x5, x7, end slt x4, x3, x4
beq x4, x0, around addi x5, x0, 0 around: slt x4, x7, x2 add x7, x4, x5 sub x7, x7, x2 SW x7, 84 (x3) lw x2, 96 (x0) add x9, x2, x5 jal x3, end addi x2, x0, 1 end: add x2, x2, x9 SW x2, 32 (x3) done : beq x2, x2, done 6. Lab Team Maximum of 3 students 7. Delivery a) HDL module files and testbench files for each module b) Each group should submit one lab report, which should cover i. The test result for each module ii. The test result of executing the testbench program provided section 5 c) Each person should submit an individual peer evaluation report, which should cover i. His/her project contribution and evaluation ii. Other team members' project contribution and evaluation 8. Evaluation a) The designed single-cycle RISC-V processor 80% b) Peer evaluation: 20%