In single cycle computer architecture, it uses 16-bit word with
ISA
(Instruction Set Architecture) shown below. This instruction
supports changes in the
sequence of instruction execution by adding an extended, 6-bit,
signed 2s-complement
address offset to the program counter (PC) value. The data in AD
Left is (I 10) and AD
Right is (100). If the PC is currently at 40, and Source Register
satisfies the jump
condition, what is the PC value to execute the next instruction in
the computer? '...
In Single Cycle Computer Architecture It Uses 16 Bit Word With Isa Instruction Set Architecture Shown Below This Ins 1 (56.92 KiB) Viewed 34 times