2.72 As we know, the emitter voltage of the CC config- uration follows the base voltage, but with an offset of about 0.7
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2.72 As we know, the emitter voltage of the CC config- uration follows the base voltage, but with an offset of about 0.7
2.72 As we know, the emitter voltage of the CC config- uration follows the base voltage, but with an offset of about 0.7 V. This offset is often undesirable, as one would rather have the dc level of the output be the same as that of the input. The circuit of Fig. P2.725 uses a pnp CC stage, whose offset is +0.7 V, followed by an npn CC stage, whose off- set is -0.7 V. The two offsets tend to cancel each other out, making the output de level identical to that at the input. In particular, if the signal source has a zero de component, so will the output. For this cancellation to be effective, we must have V BEZ = Vell. This can be achieved, for instance, if the BJTs have 1,2 = 1, and we bias them identi- cally by letting Re2 = Rg. In the circuit shown, let the BJTs have Br = Br2 = 100, V = V12 = 0, and 1,1 = 1,21 A2 12 V REL 10 kΩ Q2 Q Vsig REZ R; 10 kΩ w R RL 20 kΩ -12 V FIGURE P2.72
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