(SPI Control/Status
Registers)
Referring to Figure Q4, write a fragment of code in C to write
to the SPCR and SPSR registers of the ATMega328P microcontroller to
set it up for the following operation:
(You may ignore the SPIF and WCOL bits).
Spi Control Status Registers Referring To Figure Q4 Write A Fragment Of Code In C To Write To The Spcr And Spsr Regis 1 (469.5 KiB) Viewed 50 times
Spi Control Status Registers Referring To Figure Q4 Write A Fragment Of Code In C To Write To The Spcr And Spsr Regis 2 (170.29 KiB) Viewed 50 times
SPCR - SPI Control Register 7 6 5 4 3 2 1 0 SPCR BI 0x2C (0x4C) Read/Write Initial Value SPIE RW 0 SPE RW 0 DORD RW 0 MSTR RW 0 CPOL R/W CPHA R/W SPR1 R/W SPRO R/W 0 0 0 0 • Bit 7 - SPIE: SPI Interrupt Enable This bit causes the SPI interrupt to be executed if SPIF bit in the SPSR Register is set and the if the Global Inter- rupt Enable bit in SREG is set. • Bit 6-SPE: SPI Enable When the SPE bit is written to one, the SPI is enabled. This bit must be set to enable any SPI operations. • Bit 5-DORD: Data Order When the DORD bit is written to one, the LSB of the data word is transmitted first. When the DORD bit is written to zero, the MSB of the data word is transmitted first. • Bit 4-MSTR: Master/Slave Select This bit selects Master SPI mode when written to one, and Slave SPI mode when written logic zero. If SS is config- ured as an input and is driven low while MSTR is set, MSTR will be cleared, and SPIF in SPSR will become set. The user will then have to set MSTR to re-enable SPI Master mode. • Bit 3-CPOL: Clock Polarity When this bit is written to one, SCK is high when idle. When CPOL is written to zero, SCK is low when idle. Refer to Figure 19-3 and Figure 19-4 for an example. The CPOL functionality is summarized below: Table 19-3. CPOL Functionality CPOL Leading Edge Trailing Edge 0 Rising Falling 1 Falling Rising • Bit 2-CPHA: Clock Phase The settings of the Clock Phase bit (CPHA) determine if data is sampled on the leading (first) or trailing (last) edge of SCK. Refer to Figure 19-3 and Figure 19-4 for an example. The CPOL functionality is summarized below: Table 19-4. CPHA Functionality CPHA Leading Edge Trailing Edge 0 Sample Setup 1 Setup Sample • Bits 1,0 - SPR1, SPRO: SPI Clock Rate Select 1 and o These two bits control the SCK rate of the device configured as a Master. SPR1 and SPRO have no effect on the Slave. The relationship between SCK and the Oscillator Clock frequency fosc is shown in the following table:
Table 19-5. Relationship Between SCK and the Oscillator Frequency SPI2X SPR1 SPRO SCK Frequency 0 0 0 food 4 0 0 1 food 16 0 1 0 fosc/64 0 1 1 1 0 0 fosc/2 1 0 1 fosc/8 1 1 0 1 1 1 fosc/64 food/128 fosc/32 7 SPSR-SPI Status Register BI Ox2D (0x4D) SPIF WCOL Read Witte R Initial Value 0 0 I SPSR 1 DI ODIN R 0 R R 0 I O R 0 R 0 IO SP12X BW 0 0 O • Bit 0 - SP12X: Double SPI Speed Bit When this bit is written logic one the SPI speed (SCK Frequency) will be doubled when the SPI is in Master mode (see Table 19-5). This means that the minimum SCK period will be two CPU clock periods. When the SPI is config- ured as Slave, the SPI is only guaranteed to work at fosc 4 or lower. (You may ignore SPIF and WCOL in this question).
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