Consider the following set of MIPS instructions: LW $s1, 10($s2) ADD $s3, $s1, $t4 SUB $s4, $s1, $t4 OR $s5, $s3, $s1 LW

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Consider the following set of MIPS instructions:
LW $s1, 10($s2)
ADD $s3, $s1, $t4
SUB $s4, $s1, $t4
OR $s5, $s3, $s1
LW $s0, 40($s2)
AND $s1, $s5, $s4
SLL $s3, $s0, s4
SW $s1, 50($s2)
Assuming a 5 stage multi-cycle processor design, provide the
following:
1) Identify the data dependencies and data hazards
involved in this code.
2) A pipeline diagram of the set of instructions with no
forwarding
3) A pipeline diagram of the set of instructions assuming
forwarding