Problem 6 (30 points): When processor designers consider a possible improvement to the processor datapath, the decision

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Problem 6 30 Points When Processor Designers Consider A Possible Improvement To The Processor Datapath The Decision 1 (61.52 KiB) Viewed 80 times

Problem 6 (30 points): When processor designers consider a possible improvement to the processor datapath, the decision usually depends on the cost performance trade-offs. In the following three sections, assume that we are starting with datapath given to you: Ada Sada sum Sh Instruction 16.01 Central ALE Rez Instruction 10-15 Read register Red Instruction 124-201 data Read address Instruction 31-01 instruction memory ALU ALU Instruction 11-71 - Addresa duta Write register Write data Register . SK Data memory Instruction 131-01 64 mm Gen ALU control 30.10.12 Also the logic blocks used to implement this datapath have the following latencies: I-Mem Register Adder Mux ALU Control file D-Mem 400ps 100ps 30ps 120ps 200ps 350ps 100ps block And costs: I-Mem Adder Mux ALU D-Mem Register file 200 Control block 500 1000 30 10 100 2000 Consider the addition of a multiplier to the ALU. This addition will add 300ps to the latency of the ALU and will add a cost of 600 to the ALU. The result will be 5% fewer instructions executed since we will no longer need to emulate the MUL instruction. a) What is the clock cycle time with and without this improvement? b) What is the speedup achieved by adding this improvement?