- In This Lab You Will Design A Digital Lock The Lock Will Have Four Buttons For You To Enter A Secret Three Digit Code 1 (50.57 KiB) Viewed 30 times
- In This Lab You Will Design A Digital Lock The Lock Will Have Four Buttons For You To Enter A Secret Three Digit Code 2 (24.61 KiB) Viewed 30 times
PLEASE WRITE THE STRUCTURAL VHDL CODE FOR THE TOP-LEVEL DESIGN BY
INITIATING THE LOCK MODULE AND THE DEBOUNCING MODULE USING THE
COMPONENT/PORTMAP STATEMENTS. HAVE IT SO I CAN COPY AND
PASTE!! WILL GIVE THUMBS UP!!
In this lab, you will design a digital lock. The lock will have four buttons for you to enter a secret three-digit code to unlock it. You will use the pushbuttons BTN (3:0) on the FPGA board for this BTNO) will represent the digit '0', BTN(I) the digit '1', BTN(2) the digit '2', and BTN(3) the digit 3'. The secret code is 0-2-3. So you must press "0", followed by '2', and then 3' in order to open the lock. If you entered the correct code, LED LDO will light up to indicate that the lock is open. If the code is incorrect, L.D7 will light up instead. You must make three button pressings before you know if you have entered the correct code or not. While you are keying in the code, all LEDs will be ofl. The following is the top-level schematic of the digital lock. It consists of 2 modules - the lock module and the pushbutton debouncing module. The 'CLR input is active low and is mapped to a slide switch. The clock is to be connected to the onboard 100Mhz clock at location ws for Basys3. ZO) is mapped to LDO to indicate a correct code while z{l) is mapped to L.D7 to indicate an incorrect code. led 3:01 wp100 AL 2010 check it CKX CUR doch CUI Figure ! You need to design the state machine for the lock module. A sample state diagram is provided on the next page for a simple lock that accepts a two-digit secret code of 0-1. You can use it as a reference and modify it for your design. After this, write the behavioral VHDL code for the lock module. You can test your design by simulating it using a testbench. A sample testbench is also provided on the next page. You need to modify it to test for the correct secret code as well as an incorrect code. In your simulation, you need to display the state in the waveforms so that you can check it. The code for the debouncing module is provided on the next page: you can use it as is. In the previous lab, you must have seen the undesirable effect of a bouncing switch. Basically, when you press a pushbutton, instead of going from 0 to 1 cleanly, it may bounce back and forth between 0 and i for a few milliseconds. So a debouncing circuit is needed to prevent any errors in the circuit operations Once the modules are completed, write the structural VHDL code for the top-level design by instantiating the lock module and the debouncing module using the component/portmap statements. After this, implement the design and transfer it to the FPGA board. You will need to create a new implementation constraints file to map the signals to the pushbuttons, LEDs, slide switch, and onboard 100Mhz clock
Code for debouncing module library IEEE: use IEEE.STD LOGIC _1164.ALL: use IEEE.STD_LOGIC_ARITH.ALI: use IEEESTD_LOGIC_UNSIGNED.ALL: entity debounce is Port (clock,clr: in STD LOGIC inp:in std_logic_vector(3 downto 0); outp:out STD_LOGIC_Vector(3 downto 0)); end debounce; architecture Behavioral of debounce is signal count STD LOGIC_VECTOR (17 downto): signal clk 190 : std_logic; signal delay I, delay2, delay); std_logic_vector(3 downto): begin PROCESS (elr, clock) BEGIN IF elr = THEN count (others > 0): ELSIF Clock EVENT AND Clock = '1' THEN count = count+1: END IF : END PROCESS clk 190ccount(17): process (clr.clk 190) if cir' then delayic"OX00"; delay2c"0000"; delay3<"0000"; elsif clk 19/event and clk 190='1' then delayi cinp: delay2 cadelay; delay3<=delay2; end if end process: begin outpdelay and delay and delay 3: end Behavioral;