The D latch of Fig. 5.6 is constructed with four NAND gates and an inverter. Consider the following three her ways for o

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The D Latch Of Fig 5 6 Is Constructed With Four Nand Gates And An Inverter Consider The Following Three Her Ways For O 1 (169.13 KiB) Viewed 47 times

The D latch of Fig. 5.6 is constructed with four NAND gates and an inverter. Consider the following three her ways for obtaining a D latch. In each case, draw the logic diagram and verify the circuit operation. (a) Use NOR gates for the SR latch part and AND gates for the other two. An inverter may be needed. (b) Use NOR gates for all four gates. Inverters may be needed. (c) Use four NAND gates only (without an inverter). This can be done by connecting the output of the upper gate in Fig. 5.6 (the gate that goes to the SR latch) to the input of the lower gate (instead of the inverter output). (a) Logic diagram (b) Function table FIGURE 5.6