+ VDD = +15V 4.0 mA Cc If Rsig w 1μF 10k12 Usig RL + 1 W 100 k12 + V bias

[answerhappygod]

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For the circuit in the figure, with the FET operating in
saturation, KP = 50 mA/V2, W/L =400 mm / 10 mm, Vto = 1 V, rd ~ 25
kΩ, Rbias = 0, Cgs = 1 pF and Cgd = 1 pF, determine:
a) The maximum profit
b) The frequencies associated with the zero and the poles
c) The equivalent Miller capacitance to replace Cgd
d) Break frequency using Miller's approximation
+ VDD = +15V 4.0 mA Cc If Rsig w 1μF 10k12 Usig RL + 1 W 100 k12 + V bias