using components of full adder, D-FF, serial adder control circuit,
and 4-bit shift register. The 4-bit shift register has serial in ,
shift right, load, and clock as one bit inputs, d as 4-bit input,
and q as 4-bit output. The main design has load, start, clock as
one bit inputs, a & b as 4-bit inout. Please upload one file
that include the VHDL code as text, screen shots of RTL viewer
& Technology map viewer, and simulation results.
-- component 1 --
component Serial_Adder is
port (
st, clk:
in bit;
sh: out
bit
);
end component Serial_Adder;
-- component 2 --
component Full_Adder is
port (
a, b, cin:
in bit;
s, cout:
out bit
);
end component Full_Adder;
-- component 3 --
component FlipFlop is
port (
reset,
clk: in bit;
d: in
bit_vector (3 downto 0);
q: out
bit_vector (3 downto 0)
);
end component FlipFlop;
-- component 4 --
component Shift_Register is
port (
sr, ld,
sin, clk: in bit;
d: in
bit_vector (3 downto 0);
q: out
bit_vector (3 downto 0)
);
end component Shift_Register;
please Write the answer code and the Simulation
