1 Pla Implementation And Multiple Outputs 10 A Program The Pla To Implement The Logic Defined By The K Maps Shown 1 (82.13 KiB) Viewed 42 times
1 Pla Implementation And Multiple Outputs 10 A Program The Pla To Implement The Logic Defined By The K Maps Shown 2 (89.81 KiB) Viewed 42 times
1. PLA Implementation and Multiple Outputs (10%) a) Program the PLA to implement the logic defined by the K-maps shown. Use an "X to show a connection. Write the expression for each AND over its input lead as indicated. Do not add any AND gates. AB CD 00101010 001 AB 00 01 11 10 00 11 01 1 1 01 1 (11 1 B AB 00 011 10 00 1 1 01 1 1 B (11 d A (10 11 1 Map of G B 11 1 1 A 1101 A 1 10 Map of F Map of H C write each AND term here F G H 皮皮及皮
BE b) Assume that now you want to implement the same circuit with regular logic gates (not PLA). Revise the looping of the K-maps for this purpose and obtain the corresponding Boolean equations for F, G, and H using the heuristic approach. Minimize the number of gates. D CD AB 00011 10 001 CD AB 0001210 001 1 4 011 1 B 011 CD AB 00 0111 10 oo 1 1 011 1 (11 A 1 w 1 Map of G B 8 d 11 1 A 101 1 101 A 10 Map of H Map of F F= C HE 718
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