Load Immediate Li Instruction Decoder The Li Decoder Selects The 2x1 Multiplexer As Seen In The Fig 1 Input To The L 1 (33.24 KiB) Viewed 56 times
Load Immediate Li Instruction Decoder The Li Decoder Selects The 2x1 Multiplexer As Seen In The Fig 1 Input To The L 2 (16.15 KiB) Viewed 56 times
Load Immediate Li Instruction Decoder The Li Decoder Selects The 2x1 Multiplexer As Seen In The Fig 1 Input To The L 3 (27.41 KiB) Viewed 56 times
Load Immediate (LI) Instruction Decoder The LI decoder selects the 2x1 Multiplexer as seen in the Fig. 1. Input to the LI decoder is the 3-bit OPCODE [8:6), and the output is a l-bit value, dectomux. The output only becomes '0' when the OPCODE is '100', which means an LI instruction will be executed; otherwise, the output is 'l'. Design the LI decoder using Ternary Operator ? :'. Following is the syntax for ternary operator: <expression 1>? <expression 2> : <expression 3> If the first expression is non-zero (true), the second expression is evaluated and given as the result of the ernary expression. Otherwise, the third expression is evaluated and given as the result of the ternary expression. See the 2x1 MUX implementation example using ternary operator from Lab7_resources.pdf.
The 2x1 mux is a quadruple multiplexer (each input and output are 4-bits each) that chooses from 2 4- bit inputs. If select line is '0' then the output of the mux becomes the 10 input; otherwise, the input connected to Il becomes the output (remember 10 and I are both 4 bits, select line is 1 bit). Design the quadruple 2x1 mux using Ternary Operator.
Instruction Register (IR) OP CODE IR[8:6) IR [8:6) Load Inst. Decoder Rs A[3:0) Read_Reg 1 IR[5:4) struction [8:0) Read_data1 dectomux Result ALU Rt IR(3:2) Read_Reg 2 Register_file Read_data2 B[3:0) Rd IR(1:0) Write_Reg Write_DATA IR[5:2] 2x1 Mux (4-bit) 1 Fig 1. 4-Bit CPU
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