Q.4 The circuit shown in Figure Q.4 is a two-stage operational amplifier with differential input and output signals. Ass

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Q 4 The Circuit Shown In Figure Q 4 Is A Two Stage Operational Amplifier With Differential Input And Output Signals Ass 1 (88.69 KiB) Viewed 68 times

Q.4 The circuit shown in Figure Q.4 is a two-stage operational amplifier with differential input and output signals. Assume all transistors are operating in the saturation region and y = λ = 0 in all calculations. Ignore parasitic capacitances of the transistors (i.e. only consider CX, CY and CL). Given that the DC voltage at node X and Y, VX = VY= 1.5 V, and total power dissipation is 1.75 mW. (a) Determine the width of transistors M5, M6 and M7. (5 marks) (b) Determine the maximum resistance values for R3 and R4. (4 marks) (c) Draw the small signal model of the circuit and derive the overall voltage gain transfer function, Av(s) of the circuit. (8 marks) (d) Identify the dominant pole and calculate its value in Hertz. (4 marks) (e) Sketch with complete labelling the Bode plot of gain and phase response. (4 marks) Vo CL www R3 Cx [G= Vai o www Voo R₁ 15 Y M₂ M₂ M₁ M₂ Ms R₂ Cy VIN ww R₁ M₂ - Vo CL All L is 1 μπ W, =W₂ = 10 μm W, =W₁ = 10 μm V = 0.2 V ODS R₁ = R₂ = 20 KQ Cx=C₁ = 1 pF C=50 pF