- Attained Cep Attributes 1 Depth Of Analysis Required 2 Depth Of Knowledge Required 3 Interdependence Question Desig 1 (92.47 KiB) Viewed 25 times
Attained CEP Attributes: 1- Depth of analysis required 2- Depth of knowledge required 3- Interdependence Question: Design a standard ASIC chip for water management system in University. Water storage system is consisting of a large main underground water storage tank, which provides water to four small tanks installed on roof of A, B, C and F block of the university. Designed management system should work according to following conditions: When main water tank is almost full, green indicator light will be" ON" indicating the full condition. When main water tank is half, yellow indicator light will be" ON" indicating the half-full condition. When main water tank is close to dead level, red indicator light will be "ON" indicating danger level for necessary action. Each of the four small tanks has a separate water pumping motor to pump the water from main underground tank to that small tank (i.e. A, B, C and F block tank). In case of main underground tank having enough water above the dead level, if water level in any of the small tanks fall below a certain level, respective pumping motor will automatically be" ON" to refill the tank to a certain level. After refiling to certain level, motor will be" OFF" again. Only one motor will be" ON" at a time to fill the respective tank. If two or more tanks demands water refilling at the same time, then priority will be given in order of A, B, C and F. (i.e. if both A and B requires refiling, A will be refiled first, then B will be refiled once A is completely filled) Design logic circuit using transistor as a switch level design approach. A. Provide gate level implementation with minimum possible number of gates. Use. standard minimization techniques used in digital design to reduce the gates count. B. Develop the most efficient SCMOS transistor switch level schematic for the minimized logic obtained from part A. C. Develop the most efficient stick diagram for the layout in part B, and estimate the area in micron square D. Develop Standard cell layout and find the density of the logic E. Produce routing diagram for the standard layout