1 Consider The Following Accesses To Memory Addresses In The Given Order Below Complete The Direct Mapped Cache Table 1 (59.24 KiB) Viewed 29 times
1 Consider The Following Accesses To Memory Addresses In The Given Order Below Complete The Direct Mapped Cache Table 2 (10.18 KiB) Viewed 29 times
1. Consider the following accesses to memory addresses in the given order below. Complete the direct mapped cache table. The data entry should be represented as Mem[block#]. Create a log at the bottom of the cache table keeping tracking hits and misses. The log can be a table or a bulleted list. The cache table should show the final representation once all the addresses have been requested. 16 21 Address Binary 2 3 13 64 66 46 19 11 3 22 4 Cache Index 000 001 010 011 100 14 101 110 111 This table below represents the requested addresses with their respective blocks. Convert the address to binary representation (do not need to show the work to convert the address to binary). 6 43 11 2, 3, 16, 21, 64, 66, 46, 19, 11, 3, 22, 4, 14, 6, 43, 11 Tag Block 00000 00000 00100 00101 00011 10000 10000 01011 Valid 00100 00010 00000 00101 00001 00011 00001 01010 00010 Data
2. Explain the difference between each cache associativity. Also, provide examples per associativity using the first five requested addresses from the left from the first question for all the associativity.
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