Assume that individual stages of the data path have the following latencies. IF:250ps ID:350ps EX:150ps MEM:300ps WB:200

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answerhappygod
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Assume that individual stages of the data path have the following latencies. IF:250ps ID:350ps EX:150ps MEM:300ps WB:200

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Assume that individual stages of the data path have thefollowing latencies.IF:250psID:350psEX:150psMEM:300psWB:200ps1. What is the clock cycle time in pipilined and non-pipelinedprocessor ?
2. What is the total latency of an LW instruction in a pipelinedand non-pipelined processor ?
3. If we can split one stage of the pipelined datapath into twonew stages, each with half latency of the original stage, whichstage would you split and what is the new clock cycle time of theprocessor ?
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