need the HDL intended design,test bench code and simulation of design and test bench. deadline is today 11 :59 pm IST pl

[answerhappygod]

need the HDL intended design,test bench code
and simulation of design and test bench.
deadline is today 11 :59 pm IST
please send before the deadline time. need to
submit this assignment as soon as possible
Introduction to DL ASSIGNMENTS
CONTINUOUS EVALUATION CRITERION:
Equal weightage would be given to the following for each assignment:
3. CLASS-ASSGN: Design a system which receives 16-bit data sequentially and output even and
odd sequenced data from the fourth data point onwards. Verify the design functionally by
writing a test-bench at least for two sets of 16-bit data. You need to simulate the entire
design using the test bench.