Write Verilog code to create a 16x16 register file. The register file should have two output busses (bus A and bus B), a

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Write Verilog code to create a 16x16 register file. The registerfile should have two output busses (bus A and bus B), along withtheir corresponding bus addressing lines for each bus. The registerfile must allow loading the registers one at a time through a databus, data bus address lines, and register load signal. Provide aworking test bench as proof that your project is working along witha brief document explaining the test procedure and the resultsobtained.

Write Verilog Code To Create A 16x16 Register File The Register File Should Have Two Output Busses Bus A And Bus B A 1 (91.7 KiB) Viewed 57 times

data MemWR regDSTAddr loadEnable ROM Instruction Decoder dSelect fSelect PC busASRCAddr busBSRCAddr HazardA Hazard Detector aSelect bSelect HazardB dPrimeMuxOut 4 32 10 Register File Function Unit 0 1 2 3 4 Data Out Address Out Data In dataMemWR