Question 2 (15 points) Answer the following questions regarding timing analysis and operation of latch and flipflop. a)

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Question 2 15 Points Answer The Following Questions Regarding Timing Analysis And Operation Of Latch And Flipflop A 1 (96.79 KiB) Viewed 24 times

Question 2 (15 points) Answer the following questions regarding timing analysis and operation of latch and flipflop. a) Given the circuit diagram for F and the table of gate delays shown below, what is the contamination delay and the propagation delay for each path of the circuit? Fill in the table. To describe a path use the numbers in the gates (for example, the path from input X via gate 2 and gate 5 to output F should be noted as "X-2-5-F"). (7 points) X Gate type Z NOT OR AND Path Contamination delay 1 ns 2 ns 2 Maximum clock frequency= ns 3 Propagation delay Contamination delay 3 ns 4 ns 5 ms b) What is the contamination and propagation delay for the circuit? (4 points) Contamination delay = Propagation delay=_ ns ns Propagation delay c) Assume that inputs X, Y, Z and output F are clocked by D flip-flops with propagation delay T-= 4 ns and setup time Ts=3 ns. What is the minimum clock period T, and the maximum allowed clock frequency fmar? (4 points) MHz