Problem #1 A) Assume the following C code where elements in the same row are sorted contiguously. Assume each word is 64

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Problem 1 A Assume The Following C Code Where Elements In The Same Row Are Sorted Contiguously Assume Each Word Is 64 1 (46.04 KiB) Viewed 12 times

Problem #1 A) Assume the following C code where elements in the same row are sorted contiguously. Assume each word is 64-bit integer. for (1-0: 18: 1++) for (J-0: J<8000: J++) A[1] [J]=B[1] [0]+A[J] [: 1- How many 64-bit integers can be stored in a 16-byte cache block? 2- Which variable references exhibit temporal locality? 3- Which variable references exhibit spatial locality? B) Caches are important to providing a high-performance memory hierarchy to processors. Below is a list of 64-bit memory address references, given as word addresses. 0x03, 0xb4, 0x2b, 0x02, 0xbf, 0x58, Oxbe, 0x0e, 0xb5, 0x2c, Oxba, Oxfd 1- For each of these references, identify the binary address, the tag, and the index given a direct-mapped cache with 16 one-word blocks. Also, list if each reference is a hit or a miss, assuming the cache is initially empty. 2- For each of these references, identify the binary address, the tag, and the index given a direct-mapped cache with two-word blocks and a total size of 8 blocks. Also, list if each reference is a hit or a miss, assuming the cache is initially empty. 3- You are asked to optimize a cache design for the given references. There are three direct-mapped cache designs possible, all with a total of 8 words of data: C1 has 1-word blocks, C2 has 2-word blocks, and C3 has 4-word blocks. In terms of miss rate, which cache design is the best? If the miss stall time is 25 cycles, and CI has an access time of 2 cycles, C2 takes 3 cycles, and C3 takes 5 cycles, which is the best cache design? Many different design parameters are important to a cache's overall performance. Below are listed parameters for different direct-mapped cache designs. Cache Data Size: 32 KiB Cache Block Size: 2 words Cache Access Time: 1 cycle