224 201 2.1.2.6> You are designing a PMD and optimizing it for low energy. The core, including an 8 KB LI data cache, co

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224 201 2 1 2 6 You Are Designing A Pmd And Optimizing It For Low Energy The Core Including An 8 Kb Li Data Cache Co 1 (20.39 KiB) Viewed 65 times

224 201 2.1.2.6> You are designing a PMD and optimizing it for low energy. The core, including an 8 KB LI data cache, consumes I W whenever it is not in hier nation. If the core has a perfect L.1 cache hit rate, it achieves an average CPI of 1 for a given task, that is, 1000 cycles to execute 1000 instructions. Each additional cycle accessing the L2 and beyond adds a stall cycle for the core. Based on the following specifications, what is the size of L2 cache that achieve the lowest energy for the PMD (core, LI, 1.2, memory) for that given tak? a. The core frequency is 1 GHz, and the L.1 has an MPKI of 100 b. A 256 KB L2 has a latency of 10 cycles an MPKI of 20. a background power of 0.2 W. and each L2 access consumes 0.5 J. CAI MB L2 has a latency of 20 cycles, an MPKI of 10 a background power of 0.8 W. and each L2 access consumes 0.7 n. d. The memory system has an average latency of 100 cycles, a background power of 0.5 W. and each memory access consumes 35.