Assume the NOT gate has delay = 1 ns and all other gates havedelay = 2 ns. Initially A = B = C = 0 and D = 1; C changes to 1 at2 ns.
a) Draw a timing diagram showing the glitch due to hazard.b) Modify the circuit design to no longer have a hazard (Leave thecircuit as a two-level, OR- AND circuit.)
A D B E H
Assume the NOT gate has delay = 1 ns and all other gates have delay = 2 ns. Initially A = B = C = 0 and D = 1; C changes
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