Write An Hdl Code For The Following Specifications Write A Linear Testbench To Verify The Design Input Clk Reset N 1 (63.17 KiB) Viewed 26 times
verilog HDL code | VLSI
Write an HDL code for the following specifications. Write a linear testbench to verify the design. Input: clk, reset_n, A, B Output: AEQB, AGTB, ALTB The block has an active low asynchronous reset and works on the posedge of clock. The block takes two 4 bit numbers A,B and compares them. There are 3 single bit outputs and they are 1 in the following conditions otherwise 0. 1401 AEQB i.e. A equals B AGTB i.e. A greater than B ALTB i.e. A less than B
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