[4] Now we know the delay value for an inverter. How about the delay for 2-input NAND gate? When we compute the falling

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4 Now We Know The Delay Value For An Inverter How About The Delay For 2 Input Nand Gate When We Compute The Falling 1 (80.29 KiB) Viewed 59 times

[4] Now we know the delay value for an inverter. How about the delay for 2-input NAND gate? When we compute the falling delay of a 2-input NAND gate, we need to consider the 1.6. EXERCISES situation where two n-channel MOS transistors become ON simultaneously. This motivate us to simulate a series connection of two n-channel MOS transistors by a single n-channel MOS transistor. Determine equivalent channel width W, and channel length L, so that the single n-channel MOS transistor exactly simulates the series connection of two n-channel MOS transistors in terms of terminal voltages v.s. drain current. b High High Id THE. width Wi length L1 width Wi length L1 width W2 length L2 width W2 length L2 How about the parallel connection of two transistors? Determine equivalent channel width W, and channel length L, so that the single n-channel MOS transistor exactly simulates the parallel connection of two n-channel MOS transistors in terms of terminal voltages v.s. drain current. ? 31 width Ws length Ls width Wq length Lq