- Laboratory Exercise 2 Numbers And Displays This Is An Exercise In Designing Combinational Circuits That Can Perform Bina 1 (36.18 KiB) Viewed 88 times
- Laboratory Exercise 2 Numbers And Displays This Is An Exercise In Designing Combinational Circuits That Can Perform Bina 2 (36.18 KiB) Viewed 88 times
- Laboratory Exercise 2 Numbers And Displays This Is An Exercise In Designing Combinational Circuits That Can Perform Bina 3 (33.13 KiB) Viewed 88 times
- Laboratory Exercise 2 Numbers And Displays This Is An Exercise In Designing Combinational Circuits That Can Perform Bina 4 (47.7 KiB) Viewed 88 times
- Laboratory Exercise 2 Numbers And Displays This Is An Exercise In Designing Combinational Circuits That Can Perform Bina 5 (70.52 KiB) Viewed 88 times
- Laboratory Exercise 2 Numbers And Displays This Is An Exercise In Designing Combinational Circuits That Can Perform Bina 6 (46.82 KiB) Viewed 88 times
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Part III Figure 2 shows a circuit for a full adder, which has the inputs a, b, and G. and produces the outputs s and ca Parts band of the figure show a circuit symbol and truth table for the full adder, which produces the two-bit binary sumcos= a +b+Figure 24 shows how four instances of this full adder module can be used to design a circuit that adds two four-bit numbers. This type of circuit is usually called a ripple-carry adder, because of . the way that the carry signals are passed from one full adder to the next. Write VHDL code that implements this circuit, as described below. FA a) Full adder circuit b) Full adder symbol 0000 FA FA FA 000 00 001 0! 010 01 011 10 100 01 101 10 110 10 11111 FA Cou53 c) Full adder truth table d) Four-bit ripple-carry adder circuit Figure 2: A ripple-carry adder circuit. 1. Create a new Quartus project for the adder circuit. Write a VHDL entity for the full adder subcircuit and write a top-level VHDL entity that instantiates four instances of this full adder. 2. Use switches SW-4 and SW - to represent the inputs A and B, respectively. Use SW, for the carry-in Con of the adder. Connect the outputs of the adder.cout and S, to the red lights LEDR. 3. Include the necessary pin assignments for your DE-series board, compile the circuit and download it into the FPGA chip 4. Test your circuit by trying different values for numbers A, B, and C.
Part IV In Part II we discussed the conversion of binary numbers into decimal digits. For this part you are to design a circuit that has two decimal digits. X and Y. as inputs. Each decimal digit is represented as a 4-bit number. In technical literature this is referred to as the binary coded decimal (BCD) representation. You are to design a circuit that adds the two BCD digits. The inputs to your circuit are the numbers X and Y. plus a carry-in, Cn. When these inputs are added, the result will be a 5-bit binary number. But this result is to be displayed on 7-segment displays as a two-digit BCD sum SS. For a sum equal to zero you would display S, S. 00, for a sum of one S, So = 01. for nine Siso = 09, for ten S, So = 10, and so on. Note that the inputs X and Y are assumed to be decimal digits, which means that the largest sum that needs to be handled by this circuit is SSo = 9+9+1 = 19. Perform the steps given below. 1. Create a new Quartus project for your BCD adder. You should use the four-bit adder circuit from Part III to produce a four-bit sum and carry-out for the operation X+Y. 3 A good way to work out the design of your circuit is to first make it handle only sums (X+Y) < 15. With these values, your circuit from Part II can be used to convert the 4-bit sum into the two decimal digits S, So. Then, once this is working, modify your design to handle values of 15 < (X+Y) $ 19. One way to do this is to still use your circuit from Part II, but to modify its outputs before attaching them to the 7-segment display to make the necessary adjustments when the sum from the adder exceeds 15. Write your VHDL code using simple assignment statements to specify the required logic functions do not use other types of VHDL statements such as IF-ELSE or CASE statements for this part of the exercise. 2. Use switches SW -- and SW3-0 for the inputs X and Y. respectively, and use SW, for the carry-in. Connect the four-bit sum and carry-out produced by the operation X + Y to the red lights LEDR. Display the BCD values of X and Y on the 7-segment displays HEXS and HEX3, and display the results, so on HEXI and HEXO. 3. Since your circuit handles only BCD digits, check for the cases when the input X or Y is greater than nine. If this occurs, indicate an error by turning on the red light LEDRS. 4. Include the necessary pin assignments for your DE-series board, compile the circuit, and download it into the FPGA chip. 5. Test your circuit by trying different values for numbers X. Y and C.
Part V In Part IV you created VHDL code for a BCD adder. A different approach for describing the adder in VHDL code is to specify an algorithm like the one represented by the following pseudo-code: 1 To=A+B+ 2 if (To >9) then 3 Zo = 10: 4 c=1: 5 else 6 Z= 7 8 end if 9 So =To - Z 10 S =0 It is reasonably straightforward to see what circuit could be used to implement this pseudo-code. Lines 1 and 9 represent adders, lines 2-8 correspond to multiplexers, and testing for the condition To > 9 requires comparators. You are to write VHDL code that corresponds to this pseudo-code. Note that you can perform addition operations in your VHDL code instead of the subtraction shown in line 9. The intent of this part of the exercise is to examine the effects of relying more on the VHDL compiler to design the circuit by using IF-ELSE statements along with the VHDL > and + operators. Perform the following steps: 1. Create a new Quartus project for your VHDL code. Use switches SW - and SW 3-4 for the inputs A and B. respectively, and use SW, for the carry-in. The value of A should be displayed on the 7-segment display HEX5, while B should be on HEX3. Display the BCD sum. SS. on HEXI and HEXO. 2. Use the Quartus RTL Viewer tool to examine the circuit produced by compiling your VHDL code. Compare the circuit to the one you designed in Part IV. 3. Download your circuit onto your DE-series board and test it by trying different values for numbers A and B. Part VI Design a combinational circuit that converts a 6-bit binary number into a 2-digit decimal number represented in the BCD form. Use switches SW 5-6 to input the binary number and 7-segment displays HEXT and HEXO to display the decimal number. Implement your circuit on the DEl-SoC board and demonstrate its functionality. a