Consider the following VHDL code snippets. How do they differ?
Explain in detail.
Thank you, have a nice day.
process begin wait until (clk'event and clk='1'); if reset ='1' then a1<='0'; else a1<=D; end if; end process process (reset, clk) begin if reset='1' then b5<='0'; elseif (clk'event and clk='1'); then b5<=D; end if; end process.
Consider the following VHDL code snippets. How do they differ? Explain in detail. Thank you, have a nice day.
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