Task In your group, design and simulate a synchronous Medium Scale Integrated (MST) logie circuit with D flip-flops (DFF

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Task In Your Group Design And Simulate A Synchronous Medium Scale Integrated Mst Logie Circuit With D Flip Flops Dff 1 (40.39 KiB) Viewed 144 times

Task In your group, design and simulate a synchronous Medium Scale Integrated (MST) logie circuit with D flip-flops (DFF). The MSI circuit is one of the following: • 8xl multiplexer • 3x8 decoder • 1x8 demultiplexer • 4x2 priority encoder • 3-bit ripple carry adder 3-bit subtractor • 8-bit parity generator The MSI circuit for your group has been assigned to you see the assignment grouping file). Steps to complete the assignment: • Design the MSI circuit manually in Quartus peime using basic or universal gates (do not instantiate the component as a block). Refer to notes online resources on how to obtain the logic circuit for the component • The circuit inputs should be comnected to input ports, while cach output should be connected to DFF. All DFF should be connected to a common clock and reset. Do not design the DFF/register using logic gates, but simply instantiate the dif component from the library (primitives-storage->d). Perform the connections like the example below: CO Simulate the circuit for several values to verify correct functionality. The input values (eg. A and B) should be assigned at the negative edge of the clock, and the output (e.g. CQ) should be monitored at the positive edge of the clock. Choose any suitable clock frequency for your simulation. Note that the DFF component uses an active low reset, i.e. Q<=0 when reset = 0