Question 50 3 pts The diagram below shows the control flaw of an ALU operation controller Registers PC IR decoder clock
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Question 50 3 pts The diagram below shows the control flaw of an ALU operation controller Registers PC IR decoder clock
Question 50 3 pts The diagram below shows the control flaw of an ALU operation controller Registers PC IR decoder clock A latch 00 acc IT to all units control ALU PLA sea Blatch 2YAR MDR cc status data path address bus data bus to/from system bus Store the contents of register R2 into an address pointed by R1 Which 2 statements below are true? MAR contains value of R2 and MDR contains the value of R1. The control path instructs a head operation after MAR is updated MAR and MDR contain the value of R1. MAR contains value of R1 and MDR contains the value of R2.