Question 42 3 pts How can prefetching branch target stop pipeline stalls from happening? Make references to the figure below: Time Instruction 1 Instruction 2 Instruction 3 Instruction ...FO.NO με μερικοί ulaigiri DICO Instruction 5 HUDU Instruction 6 Instruction 7 Instruction 15 Instruction 16 Time | 92 | 9 | 10 | 11 | 12 | 141 Instruction Instruction 2 1.NO iii Ficoluyo! AWO IDEICO FOI Instruction 3 Instruction 4 Instruction 5 Instruction 6 Instruction 7 Instruction 15
Instruction 3 Instruction 4 PIDI Instructions Instruction 6 Instruction 7 Testruction 15 Instruction 16 Branch Penalty | 1 | 2 | 3 | | 5 | 6 | 7 | | 9 | 10 | 11 | 12 | 13 | 14 | Instruction ... FIND OF LAWQ Instruction 2 Instruction 3 FILCOOL Instruction 4 Instructions Instruction 6 Instruction 7 Instruction 15 Instruction 16 of instruction 4 can be prefetched in a seperate (non-conflicting) memory the pipeline stall can be avoided instruction 15 can be prefetched in a separate (non-conflicting memory the pipeline stall can be avoided If Instruction 7 can be prefetched in a separate inon-conflicting memory the pipeline stall can be avoided # Instruction 3 can be written out in a separate (non-conflicting) memory the pipeline stali can be avoided
Question 42 3 pts How can prefetching branch target stop pipeline stalls from happening? Make references to the figure b
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