Question 44 5 pts Machine A has dual port DRAM system with the same clock for both piped and unpipelined architectures.

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Question 44 5 Pts Machine A Has Dual Port Dram System With The Same Clock For Both Piped And Unpipelined Architectures 1 (41.33 KiB) Viewed 120 times

Question 44 5 pts Machine A has dual port DRAM system with the same clock for both piped and unpipelined architectures. Machine B has a single port DRAM system, but it's pipeline implementation has a 1.1 times faster clock rate. Consider Ideal CPI = 1 for both; what are their comparative speed ups when Memory Loads are 50% of the instructions executed? Comparative speed up is given by the following equation: Ideal CPI x Pipeline depth Cycle Time Speedup = unpipelined Ideal CPI + Pipeline stall CPI Cycle Time pipelined A х Speedup A/Speedup B = 1.36 Speedup B / Speedup A - 1.36 Speedup_B / Speedup A - 1.18 Speedup B / Speedup A - 1.5