Figure B1a Shows A State Diagram For A Digital Circuit That Produces A 3 Bit Pattern Assume That A Synchronous Counter 1 (67.49 KiB) Viewed 107 times
Figure B1a shows a state diagram for a digital circuit that produces a 3-bit pattern. Assume that a synchronous counter is to be designed that produces the 3-bit output sequence shown in figure B1a. Reset Figure B1a (a) Write down a state table showing the binary output sequence of the circuit, listed in the same order that they occur on the state diagram. (4 marks) (b) Briefly describe any changes to the state diagram that may be necessary, to make the design realisable . Illustrate your proposed changes by drawing a modified version of the state diagram. (4 marks) (c) Answer the following questions: How many D-type flip-flops would you need to implement the modified diagram? How many possible states are needed to be taken into account? What would be the size of the K-map? (4 marks) II
0 Reset Coster c Figure 310 Assuming that the 4-bit counter is already available and designed, make use of K- maps simplification technique, and obtain minimised sum of products Boolean equations describing the Encoder. To do that consider the counter values while circles in Figure B1b) as input in K-map and assume that any unused states can be treated as 'don't care' states. (d) Write down the equations in your answer book and attach the K-maps and draw the circuit diagram of the encoder. Use the following block instead of the counter СІК B 4-bit Counter O up to 9 с D Rst
Join a community of subject matter experts. Register for FREE to view solutions, replies, and use search function. Request answer by replying!