Question B3 Figure B3a shows the logic diagram for 4-bit shift register with D flip-flop while figure B3b shows a timing

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Question B3 Figure B3a Shows The Logic Diagram For 4 Bit Shift Register With D Flip Flop While Figure B3b Shows A Timing 1 (80.98 KiB) Viewed 36 times

Question B3 Figure B3a shows the logic diagram for 4-bit shift register with D flip-flop while figure B3b shows a timing diagram of the 'Clock' and input data 'Din' waveforms. FF2 FF3 DO Q Q Qout FFO D Q Clk > CLR FF1 D 0 Cik CLR D Q Clock D Q Clk CLR Clk CLR Reset Figure B3a Using the following module header for D flip-flop instantiation: //module header for D-type Flip-flop with asynchronous clear module DFFC(input D, CLK, CLR, output (); (a) Write an HDL Verilog code to describe the circuit in Figure B3a. Note that the circuit has three inputs: Din, Clock and Reset; and one output Qout (b) Given that the serial input data-bits applied to 'Din' change state "just after the positive edges of the 'Clock' signal, sketch the waveform for the output of flip-flop 'FF3', 'Qout' (Figure B3b). Tolka Clock Imur un Reset Din Dout Figure B3b (c) Write down a general expression for the delay between 'Din' and the nth flip-flop 'Q' output, 'Qn', in terms of 'n' and the period the clock, 'Telk', rounded to the nearest whole number of clock periods. (d) If th f the clock frequency used to drive the circuit shown in figure B3b is 2.5MHz, calculate the maximum delay that can be introduced by the circuit and state which output the delayed signal would appear on. (e) Using circuit in Figure B3a, and a 2x1 multiplexer with SEL input shown in figure B3c, draw a circuit diagram that can be used as a 4-bit shift register when (SEL = 1) or a 4-bit memory when (SEL = 0). When the circuit is in a shift register mode, it operates the same as circuit in Figure B3a. However, when the circuit is in memory mode, each flip-flop preserves its state regardless of incoming clock. 10 0 Y Y = 10 if SEL=0 Y = 11 SEL=1 SEL Figure B3c