Question B2 Table B2a shows the output sequence of a synchronous counter. The counter outputs, 'Q3..QO', are cleared to

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Question B2 Table B2a Shows The Output Sequence Of A Synchronous Counter The Counter Outputs Q3 Qo Are Cleared To 1 (76.33 KiB) Viewed 47 times

Question B2 Table B2a shows the output sequence of a synchronous counter. The counter outputs, 'Q3..QO', are cleared to logic-0 asynchronously, by asserting the 'Rsť input. With Rsť at logic-0, the counter outputs change on the positive edge of the 'Cik input. Upon reaching output state <Q3, Q2, Q1, QO>= <1, 0, 0, 0, the counter returns to state <0, 0, 0,1> and repeats the sequence as long as 'Rsť is negated. (a) Design a synchronous counter to implement the behaviour shown in table B2a, making use of the flip-flop shown in figure B2a (assume that clear (CLR) inputs is active-high). Fully record all design steps and draw labelled logic diagram of your design. D Q CIK 하는 PRst Figure B2a The counter designed in part (a) is to be described using the Verilog-HDL. Listing B2a below shows an incomplete description of the counter. Making use of module-instantiation statements. //module header for D-type Flip-flop with asynchronous clear module DFFC(input D, CLK, CLR, output 0); (b) Fill in the missing text (indicated by the dotted lines) required to complete the description of the counter. Rst Clk Q, QQQ. 1 X o o o o X 0 F 000 1 0 F 001 1 0 FO11 1 0 f 1 1 1 1 0 1 1 1 0 0 1 1 0 0 0 F1 0 0 0 Table B2a Listing B2a - Complete the listing below. module QB2a_Counter(input Clk, Rst, output Qo, Q1, Q2, Q3); wire DO, D1, D2, D3; DFF DFFO (.....); DFF DFF1......); DFF DFF21......); DFF DFF3(.....); assign DO = assign D1 = assign D2 = ....... assign D3 = endmodule Figure B2b shows a digital clock waveform. Making use of the following Verilog-HDL keywords: begin end initial forever Write down a sequential block to generate the declarations: continuous clock on signal 'Cik', given timescale 1 ns/ 1 ns reg Clk: 50 ns 50 ns Ons Figure B2b