Listing B2a - Complete the listing below. Question B2 module QB2a_Counter(input Clk, Rst, output Qo, Q1, Q2, Q3); wire D

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Listing B2a Complete The Listing Below Question B2 Module Qb2a Counter Input Clk Rst Output Qo Q1 Q2 Q3 Wire D 1 (100.33 KiB) Viewed 56 times

Listing B2a - Complete the listing below. Question B2 module QB2a_Counter(input Clk, Rst, output Qo, Q1, Q2, Q3); wire DO, D1, D2, D3; Table B2a shows the output sequence of a synchronous counter. The counter outputs, 'Q3. QO', are cleared to logic-0 asynchronously, by asserting the 'Rst' input. With 'Rst' at logic-O, the counter outputs change on the positive-edge of the 'Clk' input. Upon reaching output state <Q3, Q2, Q1, QO> = <1, 0, 0, 0>, the counter returns to state <0, 0, 0, 1> and repeats the sequence as long as Rst' is negated. DEF DFFO(......); DFF DFF1(.....); DEF DFF2......); DFF DFF3(.....); (a) Design a synchronous counter to implement the behaviour shown in table B2a, making use of the flip-flop shown in figure B2a (assume that clear (CLR) inputs is active-high). Fully record all design steps and draw a labelled logic diagram of your design. (14 marks) assign DO = assign D1 = assign D2 = assign D3 = D Q clk 0 Rst endmodule Figure B2a (8 marks) Figure B2b shows a digital clock waveform. Making use of the following Verilog-HDL keywords: The counter designed in part (a) is to be described using the Verilog-HDL. Listing B2a below shows an incomplete description of the counter. Making use of module-instantiation statements. 1/module header for D-type Flip-flop with asynchronous clear module DFFC(input D, CLK, CLR, output ); begin end initial forever (b) Fill in the missing text (indicated by the dotted lines) required to complete the description of the counter. Write down a sequential block to generate a continuous clock on signal 'Cik", given the declarations: "timescale 1 ns/ 1 ns Rst reg Clk; 1 0 0 0 0 0 50 ns 50 ns 0 0 Clk Q, QQQ. X 0 0 0 1 0 0 1 1 O 1 1 1 1 1 1 1 1 1 1 0 1 1 0 0 1 0 0 0 0 lons 0 0 Figure B2b 0 (3 marks) [B2 total: 25 marks] Table B2a-